Electronic device and operating method thereof

ABSTRACT

Electronic devices are disclosed. In some implementations, an electronic device includes a device interface to provide an interface to a host and detect link information associated with a bandwidth provided by the device interface in communicating with the host, a processor coupled to the device interface to be in communication with the host, and structured to be operable to control operations of the electronic device in response to a request received from the host through the device interface, and a clock generator coupled to provide the device interface and the processor with clock signals to be used to operate the device interface and the processor. The processor is configured to adjust frequencies of the clock signals based on the link information.

CROSS-REFERENCE TO RELATED APPLICATION

This patent document claims the priority and benefits of Korean PatentApplication No. 10-2020-0105211, filed on Aug. 21, 2020, the disclosureof which is incorporated herein by reference in its entirety.

TECHNICAL FIELD

Various embodiments of the present disclosure relate to an electronicdevice that performs an operation in response to a request of a host,and an operating method thereof.

BACKGROUND

The computer environment paradigm is transitioning to ubiquitouscomputing, which enables computing to appear anytime and anywhere. Therecent increase in the use of ubiquitous computing is leading to anincrease in the use of portable electronic devices such as mobilephones, digital cameras, and laptop computers. These portable electronicdevices generally use a memory system having semiconductor memorydevices as its data storage medium. A memory system may be used as amain memory device or an auxiliary memory device of a portableelectronic device.

Such a semiconductor-based memory system provides advantages over thetraditional hard disk drives since semiconductor memory devices have nomoving parts, and thus offers excellent stability and durability, highdata rate, and low power consumption. Examples of semiconductor-basedmemory systems include universal serial bus (USB) memory devices, memorycards, and solid state drives (SSD).

SUMMARY

The embodiments of the of the disclosed technology relate to anelectronic device that prevents unnecessary power consumption and heatgeneration by controlling clock frequencies of components thereof, andan operating method of the electronic device.

In some implementations, an electronic device includes a deviceinterface to provide an interface to a host and detect link informationassociated with a bandwidth provided by the device interface incommunicating with the host, a processor coupled to the device interfaceto be in communication with the host, and structured to be operable tocontrol operations of the electronic device in response to a requestreceived from the host through the device interface, and a clockgenerator coupled to provide the device interface and the processor withclock signals to be used to operate the device interface and theprocessor. The processor is configured to adjust frequencies of theclock signals based on the link information.

In some implementations, an operating method of an electronic deviceincludes detecting link information associated with a bandwidth providedby a device interface in communicating with a host, adjustingfrequencies of clock signals that are used to operate the electronicdevice based on the detected link information, and providing theelectronic device with clock signals having frequencies that areadjusted based on the detected link information.

In some implementations, an electronic device includes a deviceinterface suitable for supporting interfacing with a host, and detectinglink information with the host, a processor, and a clock generatorsuitable for providing the device interface and the processor with clocksignals, wherein the processor controls frequencies of the clock signalsbased on the link information.

In some implementations, an operating method of an electronic deviceincludes detecting link information with a host, and providing a hostinterface and a processor, included in the electronic device, with clocksignals having frequencies determined based on the detected linkinformation.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram illustrating an example of a data processingsystem including an electronic device based on an embodiment of thedisclosed technology.

FIG. 2 is a diagram illustrating compatibility between interfaces.

FIG. 3 is a block diagram illustrating an example of a data processingsystem including an electronic device based on an embodiment of thedisclosed technology.

FIG. 4 is a flowchart illustrating an operating method of an electronicdevice based on an embodiment of the disclosed technology.

FIG. 5 is a diagram illustrating a lookup table stored in an electronicdevice based on an embodiment of the disclosed technology.

FIG. 6 is a diagram illustrating a clock generator included in anelectronic device based on an embodiment of the disclosed technology.

DETAILED DESCRIPTION

Hereinafter, various embodiments of the present disclosure are describedbelow in detail with reference to the accompanying drawings.

FIG. 1 is a block diagram illustrating a data processing system 100including an electronic device 110 based on an embodiment of thedisclosed technology.

Referring to FIG. 1, the data processing system 100 may include a host102 and the electronic device 110 in communication with the host 102.

The host 102 may include portable electronic devices such as a mobilephone, MP3 player and laptop computer. The host 102 may also includenon-portable electronic devices such as a desktop computer, a gamemachine, a television (TV), and a projector.

The host 102 may include at least one operating system (OS), which maymanage and control overall functions and operations of the host 102, andprovide operation between the host 102 and a user using the dataprocessing system 100 or the electronic device 110. The OS may supportfunctions and operations corresponding to the use purpose and usage of auser. For example, the OS may be divided into a general OS and a mobileOS, depending on the mobility of the host 102. The general OS may bedivided into a personal OS and an enterprise OS, depending on theenvironment of a user.

The host 102 may include a host interface 104 for exchanging data withthe electronic device 110.

The electronic device 110 may perform an operation in response to arequest of the host 102. For example, the electronic device 110 mayinclude a data storage device to store data of the host 102 in responseto the request of the host 102.

The electronic device 110 may include a device interface 132, aprocessor 134 and a clock generator 140.

The electronic device 110 may exchange data with the host 102 throughthe device interface 132. The device I/F 132 may be configured toprocess a command and data of the host 102, and may communicate with thehost 102 through one or more of various interface protocols such asuniversal serial bus (USB), multi-media card (MMC), peripheral componentinterconnect-express (PCI-e or PCIe), small computer system interface(SCSI), serial-attached SCSI (SAS), serial advanced technologyattachment (SATA), parallel advanced technology attachment (PATA),enhanced small disk interface (ESDI) and integrated drive electronics(IDE).

Even though interface versions of the host interface 104 and the deviceinterface 132 are different or the numbers of lanes of the interfacesare different, the electronic device 110 and the host 102 may exchangedata therebetween. Compatibility between interfaces will be describedwith reference to FIG. 2.

FIG. 2 is a diagram illustrating the compatibility between interfaces.

FIG. 2 illustrates a maximum data transfer rate based on a PCIeinterface version and the number of interface lanes. Referring to FIG.2, the higher the interface version, the higher the maximum datatransfer rate. In addition, the maximum data transfer rate may increasein proportion to the number of lanes. In some implementations, theelectronic device 110 or the data storage device in the electronicdevice 110 may be connected to the main printed circuit board (e.g.,motherboard) of a computer system via a PCIe (peripheral componentinterconnect express). In some implementations, the electronic device110 or the data storage device in the electronic device 110 may includePCIe solid-state drives (SSDs) that are connected via PCIe to a computerfrom its peripherals to integrate flash memories directly on amotherboard of the computer.

When the interface version of the host interface 104 and the interfaceversion of the device interface 132 are different, or when the hostinterface 104 and the device interface 132 have different numbers oflanes, the maximum data transfer rates of the interfaces may bedifferent. When the maximum data transfer rates of the host interface104 and the device interface 132 are different, the host 102 and theelectronic device 110 may exchange data at a lower data transfer ratebetween the maximum data transfer rates of the host interface 104 andthe device interface 132.

For example, when a PCIe 5.0 version of the device interface 132including four lanes is connected to a PCIe 4.0 version of the hostinterface 104 including two lanes, the host 102 and the electronicdevice 110 may use two lanes as supported by the PCIe 4.0 version toexchange data therebetween. Referring to FIG. 2, even though the deviceinterface 132 supports the maximum data transfer rate of 15.75 GB/s, thehost 102 and the electronic device 110 may exchange data therebetween atthe rate of 3.94 GB/s.

FIG. 2 illustrates the compatibility between the host interface 104 andthe device interface 132, which support a PCIe protocol. However, aninterface supporting other protocols in addition to the PCIe protocolmay support backward compatibility. For example, even though the hostinterface 104 and the device interface 132 support different versions ofa USB protocol or a SATA protocol, the host interface 104 and the deviceinterface 132 may be connected using a lower version protocol toexchange data therebetween.

Referring back to FIG. 1, the processor 134 may control generaloperations of the electronic device 110 in response to a requestreceived from the host 102 through the device interface 132, and mayperform various data processing operations. The processor 134 mayperform firmware FW operations to control the operations of theelectronic device 110.

The clock generator 140 may generate a clock signal, and provide thedevice interface 132 and the processor 134 with the clock signal. Insome implementations, the clock signal may include a core clockassociated with the operating frequency of the processor 134 and/or thedevice interface 132.

As the data transfer rate of the device interface 132 increases, amaximum clock frequency required for the device interface 132 increases.In addition, a maximum clock frequency required for the processor 134also increases as the data transfer rate of the device interface 132increases and to meet the requirements of the high-performanceelectronic device 110. For example, when the electronic device 110 is amemory device for storing data of the host 102, the protocol used by theelectronic device 110 may specify requirements for read and writeoperations, according to the version and the number of lanes of thedevice interface 132. The maximum clock frequencies of the deviceinterface 132 and the processor 134 included in the electronic device110 may be determined based on the required read and write operationperformance.

As the clock frequencies of the device interface 132 and the processor134 increase, the electronic device 110 will consume more power andgenerate more heat. However, even if the device interface 132 and theprocessor 134 operate at the maximum clock frequency, the electronicdevice 110 may not exhibit the maximum performance when the deviceinterface 132 is connected to an interface having a lower version orhaving fewer lanes because the interface between the device interface132 and the host interface 104 will reduce the data processingperformance capability of the device interface 132 and the processor134. When the device interface 132 and the processor 134 operate at afixed maximum clock frequency, the electronic device 110 may consumeunnecessary power, depending on the interface version and number oflanes of the host interface 104 connected to the device interface 132.

The disclosed technology can be implemented in some embodiments toprovide a method of preventing the power consumption and heat generationof the electronic device 110 when the device interface 132 is connectedto an interface of lower version or an interface having fewer lanes.

In some embodiments of the disclosed technology, referring to FIG. 1,the device interface 132 may perform a link training operation on a linkto the host interface 104 at S102, and the processor 134 may obtain linkinformation from the device interface 132 that is trained by the linktraining operation, at S104. In some implementations, the linkinformation may include information on the version and the lane count ofthe interfaces that are connected between the host 102 and theelectronic device 110. At S106, the processor 134 may determine oradjust a clock frequency to be provided to the device interface 132 andthe processor 134, based on the link information. For example, when theprocessor 134 detects that the device interface 132 is connected to alower version interface or an interface with fewer lanes, based on thelink information, the processor may adjust the clock frequency so that aclock with a frequency lower than the maximum clock frequency isprovided to the device interface 132 and the processor 134. At S108, theclock generator 140 may provide the device interface 132 and theprocessor 134 with a clock signal with the adjusted clock frequency.

In some embodiments of the disclosed technology, the processor 134 maycontrol the clock frequencies of the device interface 132 and theprocessor 134 based on the link information, thereby preventingunnecessary power consumption and heat generation.

FIG. 3 is a block diagram illustrating an example of a data processingsystem 100 including an electronic device 110 based on an embodiment ofthe disclosed technology.

The data processing system 100 may include a host 102 and the electronicdevice 110. The host 102 and electronic device 110 of FIG. 3 maycorrespond to the host 102 and electronic device 110 described abovewith reference to FIG. 1, respectively.

The electronic device 110 shown in FIG. 3 may operate to store data forthe host 102 in response to a request of the host 102. Non-limitingexamples of the electronic device 110 may include a solid state drive(SSD), a multi-media card (MMC), a secure digital (SD) card, a universalserial bus (USB) device, a universal flash storage (UFS) device, compactflash (CF) card, a smart media card (SMC), a personal computer memorycard international association (PCMCIA) card and memory stick. The MMCmay include an embedded MMC (eMMC), a reduced size MMC (RS-MMC) and amicro-MMC, a hard disk drive (HDD), and the like. The SD card mayinclude a mini-SD card and micro-SD card.

The electronic device 110 may be embodied by various types of storagedevices. Examples of such storage devices may include, but are notlimited to, volatile memory devices such as a dynamic random accessmemory (DRAM) and a static RAM (SRAM) and nonvolatile memory devicessuch as a read only memory (ROM), a mask ROM (MROM), a programmable ROM(PROM), an erasable programmable ROM (EPROM), an electrically erasableprogrammable ROM (EEPROM), a ferroelectric RAM (FRAM), a phase-changeRAM (PRAM), a magneto-resistive RAM (MRAM), resistive RAM (RRAM orReRAM), a magnetic disk and a flash memory. The flash memory may have a3-dimensional (3D) stack structure.

The electronic device 110 may include a controller 130 and a memorydevice 150. The memory device 150 may store data for the host 102, andthe controller 130 may control data storage into the memory device 150.

The controller 130 and the memory device 150 may be integrated into asingle semiconductor device. For example, the controller 130 and thememory device 150 may be integrated as one semiconductor device toconstitute a solid state drive (SSD). In addition, the controller 130and the memory device 150 may be integrated into one semiconductordevice such as a memory card. For example, the controller 130 and thememory device 150 may constitute a memory card such as a personalcomputer memory card international association (PCMCIA) card, compactflash (CF) card, smart media (SM) card, memory stick, multimedia card(MMC) including reduced size MMC (RS-MMC) and micro-MMC, secure digital(SD) card including mini-SD card, micro-SD card and SDHC card, oruniversal flash storage (UFS) device.

Examples of the electronic device 110 may include a computer, an UltraMobile PC (UMPC), a workstation, a net-book, a Personal DigitalAssistant (PDA), a portable computer, a web tablet, a tablet computer, awireless phone, a mobile phone, a smart phone, an e-book, a PortableMultimedia Player (PMP), a portable game machine, a navigation system, ablack box, a digital camera, a Digital Multimedia Broadcasting (DMB)player, a 3-dimensional television, a smart television, a digital audiorecorder, a digital audio player, a digital picture recorder, a digitalpicture player, a digital video recorder, a digital video player, astorage device constituting a data center, a device capable oftransmitting/receiving information in a wireless environment, one ofvarious electronic devices constituting a home network, one of variouselectronic devices constituting a computer network, one of variouselectronic devices constituting a telematics network, a Radio FrequencyIdentification (RFID) device, or one of various components constitutinga computing system.

The memory device 150 may be a nonvolatile memory device and may retaindata stored therein even in the absence of power supply. The memorydevice 150 may perform a program operation to store data provided fromthe host 102, and may perform a read operation to provide data storedtherein to the host 102. In some implementations, the memory device 150may include a plurality of memory blocks each of which may include aplurality of pages, and each of the pages may include a plurality ofmemory cells coupled to a word line. In an embodiment of the disclosedtechnology, the memory device 150 may be a flash memory. The flashmemory may have a 3-dimensional (3D) stack structure.

The controller 130 may control read and write operations of the memorydevice 150 in response to a request from the host 102. For example, thecontroller 130 may provide data read from the memory device 150 to thehost 102 during the read operation, and write data provided from thehost 102 into the memory device 150 during the write operation. Thecontroller 130 may also control an erase operation of the memory device150.

The controller 130 may include a device interface 132, a processor 134,a clock generator 140, a memory interface 142 and a memory 144, whichare connected to one another through an internal bus. The deviceinterface 132, processor 134 and clock generator 140 illustrated in FIG.3 may correspond to the device interface 132, processor 134 and clockgenerator 140 described above with reference to FIG. 1, respectively.

The device interface 132 may be operated using firmware referred to as ahost interface layer (HIL).

The processor 134 may control the overall operations of the electronicdevice 110. The processor 134 may perform firmware operations to controlthe overall operations of the electronic device 110. The firmware mayinclude flash translation layer (FTL). Also, the processor 134 mayinclude a microprocessor or a central processing unit (CPU).

The processor 134 may perform operations associated with the FTL andperform foreground operations corresponding to requests received fromthe host. For example, the processor 134 may control a write operationof the memory device 150 in response to a write request from the hostand control a read operation of the memory device 150 in response to aread request from the host.

Also, the controller 130 may perform a background operation on thememory device 150. For example, the background operation may include agarbage collection (GC) operation, a wear-leveling (WL) operation, a mapflush operation, or a bad block management operation.

The processor 134 may include a register SFR. The register SFR may storeinformation necessary for the processor 134 to control an operation ofthe electronic device 110.

In some embodiments of the disclosed technology, the device interface132 may store, in the register SFR, link information associated with abandwidth for the communication between the host interface 104 and thedevice interface 132. The processor 134 may determine or adjust a clockfrequency based on the link information, and store determined oradjusted clock frequency information in the register SFR. The clockgenerator 140 may obtain the clock frequency information from theregister SFR, and generate or adjust clock signals based on the clockfrequency information and provide the clock signals to the processor134.

The memory I/F 142 may serve as a memory/data storage interface toprovide an interface to the controller 130 and the memory device 150such that the controller 130 controls the operations of the memorydevice 150 in response to a request from the host 102. When the memorydevice 150 is a flash memory such as a NAND flash memory, the memory I/F142 may generate a control signal for performing the operations of thememory device 150 and process data to be provided to the memory device150 based on control signals or instructions of the processor 134. Thememory I/F 142 may provide an interface (e.g., a NAND flash interface)for processing a command and data between the controller 130 and thememory device 150. Specifically, the memory I/F 142 may support datatransfer between the controller 130 and the memory device 150.

The memory I/F 142 may be operated by performing firmware operationssuch as operations associated with a flash interface layer (FIL) and maybe used to exchange data with the memory device 150.

The memory 144 may serve as a working memory of the electronic device110 and the controller 130, and store data such as instructions,command, parameters for operating the electronic device 110 and thecontroller 130. The controller 130 may control the memory device 150 toperform read, program and erase operations in response to a request fromthe host 102. The controller 130 may provide data read from the memorydevice 150 to the host 102, may store data provided from the host 102into the memory device 150. The memory 144 may store data required forthe controller 130 and the memory device 150 to perform theseoperations.

In some implementations, the memory 144 may include a volatile memory.For example, the memory 144 may include at least one of static randomaccess memory (SRAM) or dynamic random access memory (DRAM). In animplementation, the memory 144 may be integrated into the controller130, and in another implementation, the memory 144 is separate from thecontroller 130. In an embodiment of the disclosed technology, the memory144 may be an external volatile memory having a memory interfacetransferring data between the memory 144 and the controller 130.

As described above, the memory 144 may store data required forperforming a data write/read operation between the host and the memorydevice 150. In some implementations, the memory 144 may include aprogram memory, data memory, write buffer/cache, read buffer/cache, databuffer/cache, or map buffer/cache.

The memory 144 may store a lookup table LUT including mappinginformation between the link information and the clock frequency. Forexample, the lookup table LUT may be stored in the memory device 150,and may be loaded into the memory 144 when the electronic device 110 isbooted.

The clock generator 140 may generate a clock signal and provide theclock signal to components that need to be controlled by the clocksignal among components of the electronic device 110, such as the memoryinterface 142, the memory 144 and the memory device 150 as well as theprocessor 134 and the device interface 132.

FIG. 4 is a flowchart illustrating an operating method of an electronicdevice 110 based on an embodiment of the disclosed technology.

When power is supplied to the electronic device 110, the electronicdevice 110 may perform a booting operation at S402, S404, S406, S408 andS410.

At S402, the electronic device 110 may initialize internal hardwarecomponents of the electronic device 110.

For example, the processor 134 may initialize the host interface 132,the processor 134, the clock generator 140, the memory interface 142 andthe memory 144 based on a boot code stored in a boot loader (notillustrated) of the electronic device 110.

At S404, the processor 134 may set a clock frequency of the clockgenerator 140 to a default clock frequency.

For example, the default clock frequency may be the maximum clockfrequency of each of the host interface 132, the processor 134, thememory interface 142, the memory 144 and the memory device 150. Theclock generator 140 may provide the host interface 132, the processor134, the memory interface 142, the memory 144 and the memory device 150with a clock signal having the default clock frequency.

At S406, the processor 134 may load a firmware code, stored in thememory device 150, into the memory 144 based on the boot code. Thedevice interface 132 may perform a link training operation on the hostinterface 104 between the electronic device 110 and the host 102.

At S408, the processor 134 may detect a “link up” state.

The link up state refers to a state in which the link training operationof the device interface 132 with the host interface 104 is completed. Inthe link up state, data can be exchanged between the electronic device110 and the host 102.

As described with reference to FIG. 2, the data transfer rates of thedevice interface 132 and the host interface 104 may be limited to thelower rate of the device interface 132 and the host interface 104. Forexample, as described with reference to FIG. 2, when the deviceinterface 132 is connected to the host interface 104 having a lowerversion or fewer lanes, the data transfer rate of the device interface132 may be limited according to the interface version or the number oflanes of the host interface 104.

Upon completion of the link training operation of the device interface132, the link version and the number of link lanes between the host 102and the electronic device 110 may be determined, and the deviceinterface 132 may store link information including the link versioninformation and link lane count in a first region of the register SFR.

At S410, the processor 134 may reset the clock frequency based on thelink information.

For example, the processor 134 may access the first region of theregister SFR and obtain the link version information and the link lanecount.

The processor 134 may determine or adjust a clock frequency based on thelink information by referring to the lookup table LUT loaded in thememory 144. In addition, the processor 134 may control the clockgenerator 140 to provide the components of the electronic device 110with the clock signal that are determined or adjusted based on the linkinformation.

FIG. 5 illustrates an example of the lookup table LUT, and FIG. 6illustrates an example of the clock generator 140.

FIG. 5 is a diagram illustrating the lookup table LUT stored in theelectronic device 110 based on an embodiment of the disclosedtechnology.

The lookup table LUT may store clock frequencies of the components ofthe electronic device 110 according to the link information. FIG. 5illustrates the lookup table LUT that lists the clock frequencies of thehost interface 132, the processor 134, the memory interface 142, thememory 144 and the memory device 150, varying depending on the linkversion and the number of link lanes.

The clock frequency for each component of the electronic device 110according to the link version and the number of link lanes may bedetermined in advance. The requirements for read and write operationperformance of the electronic device 110 may vary depending on the linkversion and the number of link lanes. The clock frequency for eachcomponent of the electronic device 110 may be determined based on therequired read and write operation performance.

For example, when the link version is PCIe 4.0 and the number of linklanes is four, data may be exchanged at a maximum rate of 7.88 GB/sbetween the host 102 and the electronic device 110. The electronicdevice 110 may be designed to exhibit a maximum performance of 6.5 GB/sor higher in consideration of the bottleneck issues. The electronicdevice 110 may be designed to exhibit a sequential read performance of6.5 GB/s or higher and to exhibit a sequential write performance, arandom read performance and a random write performance which are equalto or higher than respective target performances. The target performanceof the electronic device 110 may vary depending on the link version andthe number of link lanes, and the clock frequency for each component ofthe electronic device 110 may be experimentally determined in advance inorder to satisfy the target performance for each of the link version andnumber of link lanes. For example, the clock frequency for eachcomponent of the electronic device 110 may be determined to be lower asthe link version is lowered, and may be determined to be lower as thenumber of link lanes decreases.

FIG. 5 illustrates the lookup table LUT when the device interface 132 isa PCIe 5.0 version interface including four lanes. In someimplementations, the clock frequencies may be adjusted based on thelookup table LUT. For example, when the link version is PCIe 5.0 and thenumber of link lanes is four after the link training operation on thehost interface 104, the processor 134 may increase the clock frequenciesof the components of the electronic device 110 to the maximum clockfrequency, based on the lookup table LUT. When the link version is lowerthan PCIe 5.0 or the number of link lanes is less than four as theresult of the link training operation with the host interface 104, theprocessor 134 may decrease the clock frequencies of the components ofthe electronic device 110 to a clock frequency lower than the maximumclock frequency, based on the lookup table LUT.

The processor 134 may store clock frequency information for eachcomponent of the electronic device 110 determined based on the lookuptable LUT in a second region of the register SFR. The clock generator140 may obtain the clock frequency information for each component of theelectronic device 110 from the second region of the register SFR.

Although in some implementations the device interface 132 is a PCIeinterface and is connected to the host interface 104, which is a PCIeinterface, the present disclosure is not limited thereto. In someimplementations, the device interface 132 and the host interface 104 maybe interfaces that support backward compatibility. In someimplementations, the device interface 132 and the host interface 104 maybe interfaces that support a SATA protocol or a USB protocol.

FIG. 6 is a diagram illustrating the clock generator 140 included in theelectronic device 110 based on an embodiment of the disclosedtechnology.

The clock generator 140 may include a plurality of phase-locked loopsPLL1, PLL2 and PLL3. Each of the plurality of phase-locked loops PLL1,PLL2 and PLL3 may include an oscillator for generating clock signalshaving different frequencies and a divider for dividing a clockfrequency.

The clock generator 140 may generate clock signals having various clockfrequencies, stored in the lookup table LUT, by determining a divisionratio of the plurality of phase-locked loops PLL1, PLL2 and PLL3. Forexample, the clock frequency information stored in the second region ofthe register SFR by the processor 134 may include information on aphase-locked loop which divides the clock frequency among the pluralityof phase-locked loops PLL1, PLL2, and PLL3 and a ratio by which theclock frequency is divided.

The clock generator 140 may obtain the information from the secondregion of the register SFR, and generate a clock signal to be providedto each component of the electronic device 110, by using the pluralityof phase-locked loops PLL1, PLL2, and PLL3. In addition, the clockgenerator 140 may provide the generated clock signal to each componentof the electronic device 110. FIG. 6 illustrates a case where the clocksignal generated by the clock generator 140 is provided to the hostinterface 132, the processor 134, the memory interface 142, the memory144 and the memory device 150.

As shown at S410 in FIG. 4 and FIGS. 5 and 6, when the processor 134resets the clock frequency based on the link information, the bootingoperation of the electronic device 110 may be completed.

Referring back to FIG. 4, at S412, the electronic device 110 may performa main operation based on the clock signal provided according to thereset clock frequency. The main operation, which is an operationperformed by the electronic device 110 after the booting operation isperformed, may include a foreground operation and a backgroundoperation.

In some embodiments of the disclosed technology, the processor 134 maycontrol the clock frequency of the clock signal provided to eachcomponent of the electronic device 110, based on the link informationwith the host 102. When the device interface 132 is connected to a lowerversion host interface or a narrower bandwidth host interface 104 (e.g.,the link version of the host interface is lower than the interfaceversion supported by the device interface 132, or the host interface hasfewer lanes that the device interface 132), the processor 134 may adjustthe clock frequency of the clock signal provided to each component ofthe electronic device 110 to be lower than the maximum clock frequencyof each component, thereby preventing unnecessary power consumption andheat generation of the electronic device 110. As such, performancedegradation in the electronic device 110 may also be prevented sincethermal throttling is prevented.

In some embodiments of the disclosed technology, it is possible toprevent unnecessary power consumption and heat generation by adjustingclock frequencies of components of electronic devices based on the linkversion and bandwidth (e.g., number of lanes) of the interface.

While specific embodiments have been described in the detaileddescription of the present disclosure, various changes and modificationsof the disclosed embodiments and other embodiments may be made based onthe disclosure of this patent document.

What is claimed is:
 1. An electronic device comprising: a deviceinterface to provide an interface to a host and detect link informationassociated with a bandwidth provided by the device interface incommunicating with the host; a processor coupled to the device interfaceto be in communication with the host, and structured to be operable tocontrol operations of the electronic device in response to a requestreceived from the host through the device interface; and a clockgenerator coupled to provide the device interface and the processor withclock signals to be used to operate the device interface and theprocessor, wherein the processor is configured to adjust frequencies ofthe clock signals based on the link information.
 2. The electronicdevice of claim 1, wherein the link information includes link versioninformation or link lane count or both the link version information andthe link lane count.
 3. The electronic device of claim 2, wherein thedevice interface performs a link training operation on a link to thehost by using an interface of a lower version between the deviceinterface and an interface of the host, and selects information on thelower-version interface as the link version information.
 4. Theelectronic device of claim 2, wherein the device interface performs alink training operation on a link to the host by using an interfacehaving a smaller number of lanes between the device interface and aninterface of the host, and selects the interface having the smallernumber of lanes as the link lane count.
 5. The electronic device ofclaim 2, wherein the processor adjust the frequencies of the clocksignals to use a lower frequency clock for a lower-version interface oran interface having a smaller number of lanes.
 6. The electronic deviceof claim 1, wherein the device interface performs a link trainingoperation on a link to the host during booting of the electronic deviceand detects the link information after completion of the link trainingoperation.
 7. The electronic device of claim 6, wherein the processorobtains the link information upon completion of the link trainingoperation and terminates the booting of the electronic device afteradjusting the frequencies of the clock signals.
 8. The electronic deviceof claim 1, wherein the processor adjusts the frequencies of the clocksignals based on a lookup table mapping frequencies of the clock signalsto link information.
 9. The electronic device of claim 1, wherein theprocessor further includes a register, and the device interface storesthe detected link information in the register.
 10. The electronic deviceof claim 9, wherein the processor adjusts the frequencies of the clocksignals based on the link information and stores the adjustedfrequencies of the clock signals in the register, and wherein the clockgenerator provides the device interface and the processor with the clocksignals based on the frequencies of the clock signals stored in theregister.
 11. The electronic device of claim 1, further comprising: afirst memory device including one or more data storage componentsstructured to store data; a memory interface to provide an interfacebetween the memory device and the processor; and a second memory deviceto data for operating the electronic device, wherein the clock generatorfurther provides the memory device, the memory interface and the memorywith the clock signals, and wherein the processor further adjusts theclock signals of the memory device, memory interface and memory based onthe detected link information.
 12. An operating method of an electronicdevice, comprising: detecting link information associated with abandwidth provided by a device interface in communicating with a host;adjusting frequencies of clock signals that are used to operate theelectronic device based on the detected link information; and providingthe electronic device with clock signals having frequencies that areadjusted based on the detected link information.
 13. The operatingmethod of claim 12, wherein the link information includes link versioninformation or link lane count or both the link version information andthe link lane count.
 14. The operating method of claim 13, wherein thedetecting of the link information includes: performing a link trainingoperation on a link to the host by using an interface of a lower versionbetween the device interface and an interface of the host; and selectinginformation on the lower-version interface as the link versioninformation.
 15. The operating method of claim 13, wherein the detectingof the link information includes: performing a link training operationon a link to the host by using an interface having a smaller number oflanes between the device interface and an interface of the host; andselecting the smaller number of lanes as the link lane count.
 16. Theoperating method of claim 13, wherein the providing of the clock signalsincludes adjusting the frequencies of the clock signals to use a lowerfrequency clock for a lower-version interface or an interface having asmaller number of lanes.
 17. The operating method of claim 12, furthercomprising performing a link training operation on a link to the hostduring booting of the electronic device, wherein the detecting of thelink information is performed after the link training operation iscompleted.
 18. The operating method of claim 17, further comprisingterminating the booting of the electronic device after adjusting thefrequencies of the clock signals the electronic device based on thedetected link information.
 19. The operating method of claim 12, whereinthe adjusting of the frequencies of clock signals includes adjusting thefrequencies of the clock signals based on a lookup table mappingfrequencies of the clock signals to link information.
 20. The operatingmethod of claim 12, further comprising providing a memory device, amemory interface and a memory in the electronic device with the clocksignals having the frequencies adjusted based on the detected linkinformation.